1. Field of the Invention
The present invention relates to a circuit which minimizes an offset generated in a semiconductor integrated circuit, that is, a dispersion of threshold voltage of a MOS transistor.
2. Description of the Related Art
In the semiconductor integrated circuit, due to a so-called process dispersion, an operation frequency (history effect) concerning a silicon on insulator (SOI) device, and the like, a dispersion (offset) of a threshold voltage is sometimes generated in a MOS transistor.
When the offset, that is, the dispersion of the threshold voltage of the MOS transistor is generated, an operation speed is slowed. In some cases, input data cannot accurately be detected, and erroneous data is outputted. Therefore, one of important problems is to remove or minimize the offset.
A concrete example will be described.
FIG. 1 shows a differential sense amplifier for use in a semiconductor memory.
In the semiconductor memory, data of a memory cell is often read out as a micro potential difference generated in a pair of bit lines BL1, bBL1. As is generally known, the micro potential difference is sensed and amplified by the differential sense amplifier.
Here, among the MOS transistors constituting the differential sense amplifier, when threshold voltages VthP0, VthP1 of P channel MOS transistors QP0, QP1 are different, or when threshold voltages VthN0, VthN1 of N channel MOS transistors QN0, QN1 are different, the offset is generated. This offset reduces a speed for sensing a micro potential difference of the pair of bit lines BL1, bBL1.
Moreover, when the offset increases, output data is determined only by the offset regardless of the micro potential difference generated in the pair of bit lines BL1, bBL1. As a result, a problem occurs that the input data (readout data of the memory cell) differs from the output data.
For the SOI device, one of reasons why the offset is generated in the differential sense amplifier is use frequency and history of the MOS transistor.
This reason will be described hereinafter.
FIG. 2 shows a device structure of N channel MOS transistors N0, N1 of the differential sense amplifier of FIG. 1.
Additionally, to simplify the description, it is supposed that the threshold voltages VthP0, VthP1 of the P channel MOS transistors QP0, QP1 of the differential sense amplifier of FIG. 1 are constantly equal to each other, and the threshold voltages VthN0, VthN1 of the N channel MOS transistors N0, N1 are initially equal to each other.
First, two input nodes N1, bN1 of the differential sense amplifier are precharged, and potentials are both, for example, Vdd. Thereafter, for example, data “1” is read out into the bit line BL1, and data “0” is read out into the bit line bBL1. Moreover, a sense amplifier enable signal SAEN becomes “High (=H)”.
In this case, the potential of the bit line BL1 remains Vdd, and the potential of the bit line bBL1 drops a little from Vdd. In this case, since both the potentials of the nodes N1, bN1 are higher than the threshold voltages (VthN0=VthN1) of the MOS transistors QN0, QN1, both transistors are turn on.
However, since a gate potential of the MOS transistor QN1 is a little lower than that of the MOS transistor QN0, a current flowing through the MOS transistor QN1 is a little smaller than a current flowing through the MOS transistor QN0.
That is to say, a difference of the gate potentials of the MOS transistors QN0, QN1 is a difference of currents flowing through these MOS transistors. As a result, a drop speed of the potential of the node bN1 is higher than that of the node N1.
Therefore, when the potential of the node bN1 is lower than the threshold voltage of the MOS transistor QN1, the MOS transistor QN1 is turned off, the drop of the potential of the node N1 stops, and the P channel MOS transistor QP1 is turned on.
Thereafter, the potential of the node N1 turns to a rising direction from a falling direction, and finally returns to Vdd. However, the potential of the node bN1 continues to drop, and finally indicates Vss.
When the data “1” is read out into the bit line BL1, and the data “0” is read out into the bit line bBL1, only for the N channel MOS transistors QN0, QN1, finally the current flows through the MOS transistor QN0, and the current does not flow through the MOS transistor QN1.
Here, when the sense amplifier enable signal SAEN changes to “Low (=L)”, the current does not flow through the MOS transistors QN0, QN1, but a charge remains in a substrate (body) A of the MOS transistor QN0. This charge fluctuates the substrate potential of the MOS transistor QN0, and acts in a direction in which the threshold voltage VthN0 is lowered.
Therefore, when the same data is repeatedly read out into the bit line BL1, for example, when the data “1” is repeatedly read out into the bit line BL1, only the threshold voltage VthN0 of the MOS transistor QN0 drops. Thereby, the readout speed is slowed, or an erroneous sense operation is performed.
Additionally, a frequency with which the data “1” is read out into the bit line BL1 is substantially the same as a frequency with which the data “0” is read out. In this case, a fluctuation ΔVthN0 of the threshold voltage VthN0 of the MOS transistor QN0 becomes substantially the same as a fluctuation ΔVthN1 of the threshold voltage VthN1 of the MOS transistor QN1, and there is no problem.
Moreover, the charge accumulated in a substrate A naturally disappears with an elapse of sufficient time after the differential sense amplifier is bought into an inoperative state (SAEN=“L”). However, when the operation of the differential sense amplifier is repeatedly performed, the next readout operation is started before the charge accumulated in the substrate A becomes equal to the charge accumulated in a substrate B. Therefore, as described above, the readout speed is slowed, or the erroneous sense operation is performed.
Additionally, as a technique of reducing the offset by the fluctuation of the substrate potential, a technique of connecting the substrate to a source of the MOS transistor, a technique of fixing the substrate at a constant potential, and the like have heretofore been known.
However, in any one of the techniques, it is necessary to dispose a contact portion with respect to the substrate, and therefore a problem of a drop of circuit capability due to an increase of gate capacity occurs. Moreover, any one of the techniques is effective for minimizing the fluctuation of the substrate potential of the SOI device, but it is impossible to minimize the fluctuation of the threshold voltage caused by the process dispersion.
Therefore, there has been a demand for a technique of minimizing the offset (dispersion of the threshold voltage of the MOS transistor) resulting from the process dispersion or the operation frequency of the SOI device by a circuit operational method, and preventing the drop of the operation speed or the erroneous sense operation caused by the offset.